Two-Step Reset to Reduce the SNR Drop in the LOFIC CMOS Image Sensor

A lateral overflow integration capacitor (LOFIC) complementary metal oxide semiconductor (CMOS) image sensor can realize high-dynamic-range (HDR) imaging with combination of low-noise signals and high-full-well-capacity (high-FWC) signals. However, signal-to-noise ratio (SNR) drop at the switching point between the low-noise signals and the high-FWC signals is not negligible because pixel reset kTC noise to reset small in-pixel capacitor is not canceled in the high-FWC signals. In this paper, a reset circuit for the LOFIC CMOS image sensor is presented, which reduces the pixel reset noise with additional switch and large capacitor outside the pixel array. In order to further reduce the reset noise, an asymmetric structured in-pixel reset transistor is also proposed. Since the charge flow through the channel of in-pixel reset transistor is suppressed, the pixel reset kTC noise is reduced. A test chip of the reset circuit is fabricated with a 0.18 µm CMOS process. As an evaluation result, the pixel reset noise is reduced to 556 µVrms, which is 43.0 % lower than that of the conventional LOFIC pixel. The estimated SNR drop at the switching point is 6.5 dB, which is improved by 4.2 dB.