A Review on CMP Challenges in HWB and Wafer Level Packaging

Chemical mechanical planarization/polishing process faces new challenges in multiple new dimensions as hybrid wafer bonding (HWB) and flip-chip technologies evolve to enable innovative integration forms in semiconductor applications. The advanced capabilities of (i) manufacturing the CMOS independent of the memory array through HWB and, (ii) selecting the fully functional chiplets at the die level for heterogenous components for flip-chip bonding, drive cost-effective and high-performance integration. This paper is a review of the CMP challenges as these new technologies demand additional capabilities such as bonding surface planarization in addition to TSV exposure and polishing ability for backside metallization, edge trimming as well as backside thinning. The toolsets and current capabilities are reviewed in addition to the forthcoming trends of manufacturing ultrathin wafers.