A Low-Power Open-Loop Spread-Spectrum Clock Generator Design for Ref-Clk Applications

Spread spectrum clock generation is a well-established technique for mitigating electromagnetic interference (EMI) in communication and electronic systems. This paper presents an open-loop, low-power spread spectrum clock generation circuit designed for PCIe protocol applications in the hundred-megahertz frequency range. By employing phase rotation principles, the circuit utilizes an 8-bit Current Mode Logic (CML) phase interpolator in conjunction with seed phase selection to down-convert a low-jitter PLL output clock from gigahertz to megahertz levels, achieving both power efficiency and high-precision frequency subdivision. A simple digital circuit generates an approximately 33 kHz triangular modulation waveform, enabling accelerated/decelerated frequency variations and producing spread spectrum clock signals with adjustable spread depth ($\delta$). The proposed architecture demonstrates EMI reduction of approximately 18$\mathbf{d B}, 20 ~\text{dB}$, and 22 dB in the 200 MHz output clock's power spectrum at spread depths of$1 \%, 2 \%$, and 5 %, respectively. The total power consumption is just$\mathbf{1. 6 3 5 ~ m W}$.