A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS

This paper presents a 10-bit high-speed two-stage SAR ADC. Each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. By doing this, the SAR logic delay and power are significantly reduced. A modified bidirectional single-side switching technique is used to optimize the comparator speed and offset by controlling the input common mode voltage V cm . To suppress the comparator offset mismatch induced nonlinearity, redundancy and a shared pre-amplifier are employed in the second fine stage. The pre-amplifier is implemented using a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55dB peak SNDR at 200MS/s sampling rate without any calibration. It consumes 750µW from 1.1V power supply, leading to a Walden FOM of 8.6fJ/conversion-step.