Wave Digital Emulation of an Enhanced Compact Model for RRAM Devices With Multilevel Capability

The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. This includes a wide range of applications, such as in-memory computing or memristive logic. A major advantage of the considered HfO $_{2}$ -based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem is that their fabrication still leads to device variabilities, which makes it challenging to test their functionality in an experimental fashion. This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. We aim to provide an enhanced model for multilevel capable RRAM devices, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE or VERILOG-A. Furthermore, we provide an algorithmic model, based on the wave digital (WD) concept, which allows for emulating the considered devices in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements. Finally, we extend the WD model to describe an array composed of RRAM devices for performing vector-matrix multiplication.