Substrate Shrinkage Effect on Warpage Evaluation for High Bandwidth Package on Package

High bandwidth signal transmission between ASIC and memory is more and more important especially for high performance Cell Phone Application Processor (AP) application. Several advanced packaging technologies are developed and High bandwidth Package on Package (HBPoP) is one of them to take the place of FCMAPPOP for the high/middle-end mobile phone products. The structure of HBPoP is similar as sandwich, the substrate interposer (SI) substrate is stacked on silicon top side with fine pitch solder joints to routing and re-layout the I/O and provide high bandwidth requirement. However, the warpage control is the key challenge for PoP technology due to the top side memory package and bottom side HBPoP package would be mount on mother board at the same time; especially, the thinner and thinner package thickness requirement. In this work, pretreatment temperature had apparently effect on package warpage performance, a three-dimensional computational HBPoP simulation model was developed for analyzing warpage behavior. Besides, advanced metrology analyzer (aMA) based on three-dimensional digital image correlation technology, a non-contact optical displacement measurement scheme, was used to measure bare substrate in plan strain and shrinkage behavior with different temperatures. Also, thermal mechanical analyzer (TMA) was utilized to capture the substrate shrinkage properties by multi-cycles measurement. The warpage from the simulation was verified against the experimental data. The results predicted by finite-element model (FEM) indicated that the sensitivity of parameters, including thickness and materials of each laminates and the deviation comes from different suppliers would be evaluate in this study. Moreover, several design combinations are proposed to enhance the warpage control. This work provides design guidance for HBPoP technology development.