Study on the Optimization of the Common Source Inductance for GaN Transistors

Optimization of the common source inductance of GaN-based transistors is investigated in this paper concerning different design levels, namely bond wires, package layout and PCB layout. The impact of different parameters is studied using 3D FEM field simulation. The simulation method is verified with experimental results. The contributions of bond wires, packaging and PCB layout in a half-bridge circuit to the common source inductance are separated, and a design guideline and a new chip layout are proposed to minimize the common source inductance. Final simulations show that the new chip layout is beneficial to reduce the common source inductance.