A New CBrF3 Process for Etching Tapered Trenches in Silicon

A new process for etching trenches in bulk silicon for the generation of trench capacitors in highly integrated DRAM's is reported. Trenches, 1 μm wide and up to 2 μm deep, were etched in RIE mode with using a single wafer etcher. The trenches have very smooth sidewalls. The slope of the sidewall can easily be controlled by the RF power. The possibility of tapering the trench in bulk silicon is attributed to the low selectivities of the process with regard to the oxide mask, leading to enhanced sputter etch of the mask.