Mechanism Analysis and Design of a Switched T-Type Attenuator With Capacitive Phase Compensation Technique

This letter investigates the mechanism of the phase characteristics versus frequency of the conventional and modified switched T-type attenuator cells in detail. According to the analysis, the optimal phase compensation interval for different topologies is revealed for the first time, which has important guiding significance for the design of ultralow phase error digital step attenuator (DSA) operating in different frequency bands. Furthermore, to verify the correctness and validity of the analysis, a $W$ -band 3-bit DSA was implemented in a standard 65-nm CMOS process. It achieves a measured dynamic attenuation range of 7- with 1-dB tuning step. With the help of the parallel-type capacitive phase compensation technique, the DSA exhibits a measured root-mean-square (rms) phase error of 1.1° at 90.5 GHz and phase fluctuation of only 1.6° across 85–105 GHz. Besides, the tested rms amplitude error is less than 0.6 dB. The core chip area of the designed DSA is 0.082 mm2. To the best of our knowledge, the effectiveness of parallel-type phase compensation technique based on switched T-type is first verified in $W$ -band.