Two-Transistor Metal–Ferroelectric–Metal Field-Effect Transistor (2T-MFMFET) for Scalable Embedded Nonvolatile Memory—Part II: Experiment

The key design concepts of the two-transistor metal–ferroelectric–metal (MFM) field-effect transistor (2T-MFMFET) are successfully validated experimentally. The 2T-MFMFET was fabricated using the back-end-of-line (BEOL) MFM integrated with the 0.18- $\mu \text{m}$ standard CMOS technology. Important factors for designing a sufficient memory window at low operating voltages, namely, the area ratio (AR) tuning between the ferroelectric (FE) capacitor and the readout transistor and the write/read voltage, are discussed. Due to the low operating voltage used, the retention and endurance of 2T-MFMFET are further investigated to understand the effects of FE switching in a minor polarization–voltage ( ${P}$ – ${V}$ ) loop. A write voltage pulse of 2 V and 100 ns is sufficient to ensure excellent retention of at least 10 years at 85 °C and endurance of at least $10^{{10}}$ cycles with a threshold-voltage shift window of at least 0.64 V in a device without full optimization. From both the theoretical and experimental analysis, 2T-MFMFET shows promising potential as a BEOL compatible, high-density, low-voltage embedded nonvolatile memory (eNVM) technology with robust reliability.