Design and Experimental Demonstration of 1 cm 2 Chip Size, 6.5 kV 4H-SiC MOSFETs with Current Spreading Layer

High-voltage (>3.3 kV) 4H-SiC MOSFETs represent the next critical development stage for SiC power devices, yet they introduce new design and fabrication challenges. The low doping concentration in the drift region necessitates careful JFET design: excessively narrow JFET regions as that in low-voltage-rated SiC MOSFETs drastically increase on-resistance, while widening them elevates electric field stress on the gate oxide. The adoption of Current Spreading Layer (CSL) design can effectively mitigate this trade-off. In this work, parameters such as CSL concentration, depth, and JFET width were designed and optimized through TCAD simulation. A 6.5 kV-rated 4H-SiC MOSFET with current spreading layer was successfully fabricated, with a on resistance (Ron) of 79.55 mΩ and a breakdown voltage of 7968V. And the fabricated MOSFETs demonstrate excellent electrical performance for large scale devices, with an active area of 0.73 cm² and a die size of 1 cm², which achieves the largest chip size reported to date among 6.5 kV-rated SiC MOSFETs. In addition, this study also compared devices with different gate oxide thicknesses and found that the threshold voltage and capacitance of the devices had significant differences, but almost did not affect the on resistance, especially for high-voltage-rated SiC MOSFETs such as 6.5 kV-rated.