Metal Boundary Effect Mitigation by HKMG Thermal Process Optimization in FinFET Integration Technology

In this work, the influence of high- ${k}$ /metal gate (HKMG) thermal processes such as post dielectric annealing (PDA), post metal annealing (PMA), and post amorphous Si cap annealing (PCA) on metal boundary effect (MBE) in FinFET is investigated. It is revealed that the PDA temperature increase leads to more severe MBE. On the contrary, the increase of soak or spike temperature of PMA is beneficial to reduce MBE. A higher PCA spike temperature also reduces MBE. It is demonstrated that by using an optimized combination of these three anneals, the threshold voltage ( ${V}_{\text {t}}{)}$ shift induced by MBE can be reduced by about 50% without sacrificing device performance and reliability.