P‐6.1: Research on Screen Splitting of 8T1C Pixel Circuit

The 7T1C (7 Thin Film Transistors and 1 capacitor) pixel circuits, prevalent in LTPO (Low‐Temperature Polycrystalline Oxide) products, encounter output characteristic shifts when the DTFT (Driver Thin Film Transistor) is biased for extended periods at 1Hz. This shift facilitates a noticeable brightness disparity between the hold frame and the write frame. To mitigate the 7T1C pixel circuit defects, the 8T1C (8 TFT and 1 capacitor) pixel circuit has been developed, introducing T8 to reset the source or drain of DTFT at high frequencies, thus alleviating low‐frequency flicker. In deploying the 8T1C pixel circuit, a high‐frequency signal initializes the OLED (Organic Light Emitting Diode) anode. When this signal scans into the blanking area, the driven row number decreases, reducing the load on the GIP (Gate in Panel) signal and VREFN2 signal. This more comprehensive anode initialization can lead to dark mura and screen splitting. This study explores the 8T1C pixel circuit's split‐screen issue, analyzing the mechanism, related factors (such as anode initialization voltage, the number of blank lines, and T8's brightness and reset frequency), and their impact on the split‐screen phenomenon. Employing the demura function of DDIC (Display Driver Integrated Circuit) and analyzing related factors, a solution for screen splitting is proposed. The existing demura solution is enhanced by incorporating low‐brightness photography and adjusting VREFN2 and the number of blank lines, improving the low‐brightness photography effect and optimizing the screen splitting issue.