Enabling faster VSB writing of 193i curvilinear ILT masks that improve wafer process windows for advanced memory applications

In advanced semiconductor memory manufacturing, mask and lithography are critical for patterning. In this paper we jointly study the benefits of a full-chip, curvilinear, stitchless inverse lithography technology (ILT) with mask-wafer cooptimization (MWCO) for memory applications. The full-chip ILT technology employed in this study, first demonstrated in a paper presented at the 2019 SPIE Photomask Technology Conference[20], produces curvilinear ILT mask patterns without stitching errors, and with process windows enlarged by over 100% compared to the OPC process of record. At the 2020 SPIE Advanced Lithography conference, a new method was introduced, in which mask-wafer cooptimization (MWCO) is performed during ILT optimization[22]. This new approach enables curvilinear ILT for 193i masks to be written on variable-shaped beam (VSB) mask writers within a practical, 12-hour time frame, while also producing the largest process windows. This new study presents the mask and wafer results using MWCO. Curvilinear ILT mask patterns written by VSB mask writer and the corresponding 193i process wafer prints are shown. Evaluations of mask write times, and mask quality in terms of CD uniformity and process windows are also presented.