Analog hyperbolic tangent function generator using CMOS translinear loop for on-chip activation in low-power edge inference accelerators

While digital neural-network accelerators dominate the literature, their energy per inference operation remains orders of magnitude above what a purely analog activation function could achieve if it matched the mathematical precision of its digital counterpart. This research presents an analog hyperbolic tangent (tanh) function generator built from a four-transistor CMOS translinear loop that converts a differential input voltage into a current-mode tanh output, designed for direct insertion between the multiply-accumulate array and the next layer’s input in a mixed-signal edge inference accelerator. The circuit was implemented in a 180 nm CMOS process and simulated with Cadence Spectre across five process corners and a 300-run Monte Carlo campaign. At 0.8 V supply and 2 µA bias, the generator consumed 4.7 µW and produced a tanh transfer characteristic with a root-mean-square error of 0.37% relative to the ideal mathematical function over the input range ±3 V_T. The correlation coefficient between the analog and ideal curves was 0.9997 across 25 uniformly spaced input points. The translinear core accounted for 41.3% of the total power, with bias generation and output buffering contributing 27.8% and 22.6% respectively. The circuit occupies 310 µm² and achieves a throughput of 25 million activations per second, making it a viable drop-in replacement for digital look-up-table-based tanh units in sub-milliwatt edge devices.