Single Event Upset In CMOS Static Ram And Latches

Single event upset (SEU) susceptibility due to high-energy ion hits on static RAM (SRAM) cells and various latch designs is evaluated using the two-dimensional circuit/transport SIFCOD code. Typical simulations involve as many as seven transistors, simultaneously solved using finite difference techniques on a high speed computer. Areas of SEU-susceptibility are identified on both the SRAM and latch designs. Experimental agreement for SRAM is achieved only with a parameter adjustment due to a 2D-3D effect. This parameter does not scale with device size as expected from physical models.