Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of parasitic internal fringe capacitance on\nthreshold voltage in high-K gate dielectric SOI MOSFETs is developed. Our model\nincludes the effects of the gate dielectric permittivity, spacer oxide\npermittivity, spacer width, gate length and width of MOS structure. A simple\nexpression for parasitic internal fringe capacitance from the bottom edge of\nthe gate electrode is obtained and the charges induced in the source and drain\nregions due to this capacitance are considered. We demonstrate an increase in\nsurface potential along the channel due to these charges resulting in a\ndecrease in the threshold voltage with increase in gate dielectric\npermittivity. The accuracy of the results obtained using our analytical model\nis verified using 2-D device simulations.\n