Fatigue und Imprint an ferroelektrischen Dünnschichten

Ferroelectric random access memory (FeRAM) is because of its combination of non-volatile data storage and low-energy operation a promising device to provide large scale, high-speed memories for mobile applications. Using a similar architecture as conventional DRAM memory devices, FeRAM utilizes a ferroelectric material instead of a pure dielectric material with its storage capacitor. In order to create a new and more comprehensive model for the ferroelectric fatigue, PZT samples on electrode made of Platinum, IrO2 and SrRuO3 were thoroughly investigated. Besides the influence of amplitude, frequency and signal shape on the loss of polarization, ways to renew the polarization were examined. Experiments with series of applied amplitude showed that for samples driven with strong enough voltage to reach a saturated polarization state (V > 2xVc) no dependency between fatigue and applied voltage is observed. A sample only switch with a voltage below its coercive voltage (V < Vc) showed no fatigue at all. An influence from the applied voltage on the fatigue could only be observed if the applied voltage ranges from the simple coercive voltage to the double coercive voltage. Experiments with different signal rise times could show for the first time that a lower rise time results in a faster fatigue. To explain the observed data a new model for the fatigue was introduced. With each switching cycle of a ferroelectric domain, the ferroelectric polarization start growing at seeds at one side of the capacitor expanding at limited speed throw the ferroelectric thin film towards the opposing side. During this expansion the foremost area of the switching domain creates a large unshielded electric field. When the expansion come in close proximity of the opposing electrode, high electric fields allow for electrodes to be injected into the expanding domain. The injected electrodes stop the further expansion of the domain and also averts further switching of this domain. The amount of injected charge and thereby also the amount of pinned domains is related to the injection current density as well to the effective switching time. The introduced model explains the observed data and allows to examine fatigue independent of the material properties of the ferroelectric material. Ferroelectric imprint was researched in depth with regard to ferroelectric layer thickness and thickness of a dielectric interface layer. It could be verified that, like predicted in the Grossmann model, with increasing sample thickness the shift of the coercive voltage Vc also increases. However, the shift of the coercive electric field is decreasing with increasing sample thickness. With addition experiments creating dielectric interfaces of controlled thickness it was possible to identify the electric field inside the ferroelectric layer as the driving force for ferroelectric imprint. This is opposing former results that found the electric field inside the interface to be the driving force. To explain the observed data a new model was introduced (Three-Phase-Model). The introduced model is derived from the Arlt-Model to explain ferroelectric imprint at ferroelectric thick films. The Arlt-Model mathematically describes the influence of not ferroelectric, yet polar inclusion (defects) inside the ferroelectric material. Altering the equations to regard thin films and also regard dielectric interface layers near the electrodes it was possible to find an expression that predicts ferroelectric imprint for thin films. Concluding, a new, Silicon-CMOS compatible, ferroelectric material is introduced and characterized. For the first time it could be shown that HfxSiyO2 exhibits ferroelectric as well as piezoelectric properties. The introduced models for ferroelectric fatigue and imprint allow to regard those two failure mechanisms without knowing specific material properties, enabling to determine optimum properties for specific applications. With demonstrating the ferroelectric properties of HfxSiyO2 a materials is introduced that can be integrated into existing Silicon CMOS processes without problems.