AlScN-based Ferroelectric Memcapacitor on Silicon Platform

We report an experimentally realized silicon-integrated AlScN-based ferroelectric memcapacitor (FMC) with a metal-ferroelectric-semiconductor (MFS) structure, whose underlying physical mechanism is elucidated through TCAD simulations. The FMC exhibits a distinct capacitance memory window (CMW) at zero bias with a stable high/low capacitance state (HCS/LCS) ratio of ~ 124%, enabling eight uniform and tightly spaced capacitance states for 3-bit storage. Furthermore, by utilizing non-destructive read operation (NDRO) to decouple read from write operations, the FMC achieves read-endurance surpassing write-endurance by > 4 orders of magnitude, with ultra-low read energy consumption of sub-fJ/μm2. This work presents a low-power wurtzite ferroelectric memory with promising potential for silicon-based large-scale memory and read-intensive applications.