Analysis of pn Junction Deep Trench Isolation with SU-8/SiO2-Liner Passivation in a Linear Butt-Coupled 3D CMOS Si Photodetector Array

The realization of 30 µm-deep trench isolation in a linear array of butt-coupled 3D CMOS silicon photodetectors is investigated by implementing the formation of a shallow n+-p junction and SiO2-liner over the trench sidewalls as well as the SU-8 filling trenches for passivation. The dependency of the dark I-V curve on the trench isolation scheme is analyzed by monitoring the dynamic dark I-V measurements of four samples including the schemes of single-trench isolation with different widths and the scheme of double-trench isolation. The highest and the lowest dark currents are measured in the detectors with the widest single-trench isolation and the double-trench isolation, respectively.