Root Cause Stencil Design for SMT Component Thermal Lands

ABSTRACT Recent studies on stencil design to minimize voiding on quad flat no lead (QFN) thermal lands suggest higher paste volumes create lower voiding percentages. However, volume must be reduced to eliminate the possibility of float during reflow. Thermal land stencil designs on components other than QFN’s must also reflect a reduction in printed volume to eliminate float while minimizing void percentages. The IPC 7525B Stencil Design Guideline [1] recommends a 20% to 50% reduction in the printed area of the thermal/ground plane for leadless chip carrier (LCC) / bottom terminated component (BTC) devices which is a very broad window. This guideline also recommends the window pane design for printing these thermal lands but does not specify the size of the gaps between panes. It also does not specify how close these panes can be printed to the edge of the thermal land without creating shorts to the perimeter leads or creating solder balls on components such as Decawat Packages (D-Pak). This window pane stencil design remains the most used design for the reduction of paste on thermal pads as many other designs such as rounds, diamonds, diagonal pads etc. have not been shown to dramatically impact voiding percentages. This paper specifically explores the effect of the window pane design on void area percentage after reflow for surface mount technology (SMT) component thermal pads without introducing float to the component. Specific window pane gap sizes, total area printed and distance of the outer pane edges to the copper thermal land edge will be varied to determine guidelines for thermal pad stencil design.