共栅
锁相环
丁坝
相位频率检测器
充电泵
重置(财务)
CMOS芯片
材料科学
相位检测器
探测器
物理
电压
电气工程
相(物质)
光电子学
工程类
电容器
放大器
结构工程
金融经济学
经济
量子力学
作者
M Divya,Kumaravel Sundaram
标识
DOI:10.1016/j.aeue.2023.155098
摘要
In a phase-locked loop (PLL), a high reset pulse width in the phase frequency detector (PFD) and current mismatches in the charge pump (CP) are the major contributors to a high reference spur in a clock. This paper presents a novel replica technique based dead zone free PFD to reduce the reset pulse and a self-cascode current-splitting CP to reduce current mismatch. The proposed PFD and CP are designed using the UMC 180 nm CMOS process. The proposed PFD achieves a reset pulse width of 113 ps. The CP is designed for a CP current of 100 μA. It has an output voltage range of 0.4 V–1.2 V, with a current mismatch of 1.3%. A PLL with the proposed PFD+CP achieves a reference spur that is 39.5% lower than the reference spur of the PLL with conventional PFD+CP. The proposed PFD+CP consumes 0.28 mW power in the locked stated. The layout area consumed by the proposed PFD+CP is 46 × 75 μm2.
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