电压基准
阈下传导
电气工程
电压
CMOS芯片
带隙基准
温度系数
线路调节
MOSFET
晶体管
材料科学
补偿(心理学)
过驱动电压
跌落电压
阈值电压
分压器
电源抑制比
电子工程
低压
电压倍增器
灵敏度(控制系统)
功率(物理)
工程类
光电子学
节点(物理)
功率半导体器件
工艺角
输入偏移电压
低功耗电子学
直线(几何图形)
电容器
上拉电阻器
温度测量
电压补偿
作者
Reddy Harshith,Arora Pankaj
标识
DOI:10.48550/arxiv.2508.15729
摘要
This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node using low voltage threshold (LVT) transistor models. The voltage reference leverages subthreshold operation and near-weak inversion characteristics, backed by an all-region MOSFET model. The proposed design achieves a very low operating supply voltage of 0.5 V and a remarkably low temperature coefficient of 16.28 ppm/$^\circ$C through the mutual compensation of CTAT, PTAT, and curvature-correction currents, over a wide range from -40 $^\circ$C to 130 $^\circ$C. A stable reference voltage of 205 mV is generated with a line sensitivity of 1.65 %/V and a power supply rejection ratio (PSRR) of -50 dB at 10 kHz. The circuit achieves all these parameters while maintaining a good power efficiency, consuming only 0.67 $μ$W.
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