A high throughput cyclic redundancy check VLSI architecture for VVC intra block copy

Versatile Video Coding (VVC) introduces more coding tools to improve compression efficiency compared to its predecessor High-Efficiency Video Coding (HEVC). Intra Block Copy (IBC), a coding tool for screen content, has attracted a lot of attention. IBC uses the hash-based search algorithm that significantly improves the compression of screen content. However, the corresponding calculation is complex and intensive. To solve this problem, this paper optimizes the computing process of CRC in IBC and then analyzes the relationship between the area and throughput of a lookup table. Next, a CRC hardware architecture for motion estimation of IBC is proposed. To achieve high throughput, it adopts 16 bits parallel scheme. The hardware implementation was synthesized using GF 28nm process. The measured throughput can reach 4K@60fps at 527MHz, with a gate count of 47.9k and SRAM consumption of 256 KB. The proposed hardware can meet the requirement of real-time video coding.