Complementary Two-Dimensional Vertical Transistors through Lamination with a van der Waals Metal

Vertical transistors, with the channel material sandwiched between graphene and metal electrodes, are promising for the development of next-generation electronic devices. However, realizing complementary transport in two-dimensional vertical transistors is challenging due to the significant disorder and severe Fermi-level pinning effects at the metal-semiconductor interface caused by conventional metallization. Here, we report complementary vertical transistors in graphene/${\mathrm{WSe}}_{2}/$van der Waals metal heterostructures. In this device, the van der Waals metal retains the pristine nature of atomically thin ${\mathrm{WSe}}_{2}$, minimizing the Fermi-level-pinning effect at the metal-${\mathrm{WSe}}_{2}$ interface. Thus, the barrier height and the type of majority carrier can be simply controlled by the metal work function. Based on this approach, we achieve n- and p-type ${\mathrm{WSe}}_{2}$ vertical transistors by laminating $\mathrm{Ag}$ and $\mathrm{Pt}$ as van der Waals contact metals, respectively. Moreover, with highly controllable device polarities, we demonstrate a complementary inverter by integrating two vertical transistors with different polarities. Our work not only enables complementary two-dimensional vertical transistors, but also provides a promising strategy for controlling the polarity of carriers in vertical heterostructures.