卷积神经网络
绝热过程
旁道攻击
电荷(物理)
计算机科学
功率(物理)
物理
算法
量子力学
人工智能
密码学
作者
Anjana Jyothi Banu,A. Prathiba,S. Shyam Krishna,Suraj Peddhibhotla,V. S. Kanchana Bhaaskaran
标识
DOI:10.1002/9781394261727.ch41
摘要
Cipher implementations offering security to smart grid infrastructure are vulnerable to the side channel attacks; the most popular being is the power analysis attack. Circuit level protections promise security in the lower level of abstraction. Deep learning architecture to explore the efficacy of secure adiabatic logic style-based VLSI implementation against power analysis attacks is the motive of this paper. CNN modeling of the power attack on the round 1 intermediate stage single layer PRESENT S-box byte implementation of the secure Charge Balancing Symmetric Pre-Resolve Adiabatic Logic (CBSPAL) has been attempted. Evaluation of the Side Channel Attack (SCA) has been analyzed through guessing entropy convergence. Critical Difference plot of ranks of various activation functions of CNN models for comparison among the models with hyperparameter variations have been carried out using two different keys of the S-box byte implementation. The feasibility of using 9-class and 256-class classifier for side channel power attack using CNN model with the Hamming Weight leakage model and the real-value leakage model has been attempted. The proposed SCA classifier attains guessing entropy not close to zero demonstrating the attack resistance of CBSPAL logic. The paper presents a byte-based side channel power attack on the PRESENT lightweight block cipher circuit, using UMC 90 nm technology library through industry standard Cadence® EDA tool suite.
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