FPGA Implementation of Novel Triple Data Encryption Standard for High Speed Network Security Comparison with DES

Aim: This research presents the implementation of Novel Triple Data Encryption Standard (Novel Triple DES) on Field-Programmable Gate Arrays (FPGAs) for high-speed network security. The proposed implementation is compared with the traditional Data Encryption Standard (DES) to demonstrate the improved security and performance of Novel Triple DES. Materials and Methods: The proposed Novel Triple DES implementation on FPGAs is tested using a Xilinx Virtex-7 device and compared to the traditional DES algorithm using simulation tools and performance metrics, such as encryption/decryption time and time delay analysis. The implementation requires a computer with VHDL synthesis tool and Modelsim software. The encryption and decryption processes are implemented in VHDL, while the key generation is executed using Modelsim. A time delay analysis and power consumption was conducted using 10 sample data sets, with an equal number of samples from two groups, and the results were compared using G-power with a 95% confidence interval. The research was conducted with alpha and beta set at 0.05 and 0.2. Results: In the proposed Novel Triple DES implementation, it was found that the time taken to encrypt a text data was 33.6 nanoseconds and the power consumed was 0.254 Watts. In comparison, the traditional DES algorithm had a time delay of 44.3 nanoseconds for text data encryption and consumed 0.467 Watts of power. The significance value obtained was 0.0249 which is (P< 0.05). Conclusion: These results demonstrate a significant improvement in terms of both processing speed and energy efficiency for the Novel Triple DES implementation compared to the traditional DES algorithm.