炸薯条
中间层
材料科学
薄脆饼
光电子学
计算机科学
物理
纳米技术
电信
蚀刻(微加工)
图层(电子)
作者
Ping-Jung Huang,Chin Lung Lu,Wen-En Wei,Catherine Chiu,Kong Ting,Clark Hu,Chung-Hung Tsai,S. Y. Hou,W.C. Chiou,C. T. Wang,Douglas Yu
出处
期刊:Electronic Components and Technology Conference
日期:2021-06-01
被引量:26
标识
DOI:10.1109/ectc32696.2021.00028
摘要
Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate multiple chips of SoC, chiplet, and 3D stacks such as high bandwidth memory (HBM). The interposer size increases steadily over the past few years, from one full reticle size (~830 mm 2 ) to two reticle size (~1700 mm 2 ). The growth of interposer size offers more integration power to accommodate more active silicon in a package to satisfy the HPC/AI needs. In this paper, we report the new 5 th generation CoWoS-S (CoWoS-S5) based on a Si interposer as large as three full reticle size (~2500 mm 2 ) by a novel 2-way lithography stitching approach. This will accommodate a multiple of logic chips at a total area of 1200 mm 2 (with chiplets) together with eight HBM stacks. Besides the dimensional increase of the Si interposer, new features are incorporated to further enhance the electrical and thermal performances of CoWoS-S5 compared with the previous CoWoS-S portfolio. These include an integrated deep trench capacitor (iCap) for enhanced power integrity, 5 layers of sub-micron Cu interconnect with reduced sheet resistance to satisfy high speed die to die interconnect, new TSV structure interposer for both return and insertion loss reduction, and a higher thermal conductivity thermal interface material (TIM) to achieve a lower thermal resistance. Component level reliability with excellent electrical and physical results are also discussed.
科研通智能强力驱动
Strongly Powered by AbleSci AI