Maintaining Moore’s law: enabling cost-friendly dimensional scaling

Moore's Law (Moore's Observation) has been driving the progress in semiconductor technology for the past 50 years. The semiconductor industry is at a juncture where significant increase in manufacturing cost is foreseen to sustain the past trend of dimensional scaling. At N10 and N7 technology nodes, the industry is struggling to find a cost-friendly solution. At a device level, technologists have come up with novel devices (finFET, Gate-All-Around), material innovations (SiGe, Ge) to boost performance and reduce power consumption. On the other hand, from the patterning side, the relative slow ramp-up of alternative lithography technologies like EUVL and DSA pushes the industry to adopt a severely multi-patterning-based solution. Both of these technological transformations have a big impact on die yield and eventually die cost. This paper is aimed to analyze the impact on manufacturing cost to keep the Moore’s law alive. We have proposed and analyzed various patterning schemes that can enable cost-friendly scaling. We evaluated the impact of EUVL introduction on tackling the high cost of manufacturing. The primary objective of this paper is to maintain Moore’s scaling from a patterning perspective and analyzing EUV lithography introduction at a die level.