An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2V

Low-DropOut (LDO) regulators are one of the most essential and critical analog blocks in power management of System-on-Chip (SoC) design. In this work, we present an external capacitor-less LDO voltage regulator design implemented in 45nm technology. The proposed design eliminates the resistive feedback network with a transistor which allows more control over output voltage and improve the transient response and PSRR. The design consists of Error Amplifier (EA), one common-source (CS) stage, one buffer stage and 2 pass transistors which offers a wide range of output voltage ranging from 0.4V-1.2V with an input voltage of 1.8V. The design also ensures low power operation with 7.824uA quiescent current. Furthermore, the design incurs minimum area of 0.0149mm ² and voltage overhead of 25mV(max) along with a stable output voltage with less than 1mV ripple. The schematic and layout designs are implemented and simulated in Cadence Virtuoso using 45nm bulk CMOS process.