1.2 kV 4H‐SiC planar power MOSFETs with a low‐K dielectric in central gate

Abstract A 1.2 kV 4H‐SiC planar power MOSFET with a low‐K dielectric in central gate (LK‐MOS) is proposed in this paper. The LK‐MOS features a P+ shielding region and a thick low‐K dielectric layer under the central gate. The insulation layer capacitance is reduced by the thick low‐K dielectric, while the depletion layer capacitance is decreased due to the reduced gate‐to‐drain overlap. The LK‐MOS is demonstrated to have 97.8%, 70.6%, and 52.2% lower HF‐FOM ( R on × C gd ), and 98.9%, 97.4%, and 69.4% lower HF‐FOM ( R on × Q gd ), when compared with that of the conventional MOSFET (C‐MOS), Buffered‐Gate MOSFET (BG‐MOS) and Thick Central Oxide MOSFET (TCOX‐MOS), respectively. Besides, the LK‐MOS can also have 16.8%, 5.9% lower C gs , and 19.9%, 12.4% lower Q gs compared with that of BG‐MOS and TCOX‐MOS.