锁相环
DPLL算法
相位噪声
dBc公司
计算机科学
CMOS芯片
电子工程
探测器
相位检测器
查阅表格
噪音(视频)
PLL多位
抖动
控制理论(社会学)
算法
电气工程
工程类
电信
电压
控制(管理)
人工智能
程序设计语言
图像(数学)
作者
Luca Bertulessi,Dmytro Cherniak,Mario Mercandelli,Carlo Samori,A.L. Lacaita,Salvatore Levantino
出处
期刊:IEEE Transactions on Circuits and Systems I-regular Papers
[Institute of Electrical and Electronics Engineers]
日期:2022-05-01
卷期号:69 (5): 1858-1870
被引量:4
标识
DOI:10.1109/tcsi.2022.3146788
摘要
This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115 $\mu \text{s}$ , overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL.
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