Analysis of ESD capability of SiC MOSFET with various cell designs

Abstract The electrostatic discharge (ESD) test is conducted to evaluate the reliability of metal oxide semiconductor field effect transistors (MOSFETs). When an ESD pulse is applied to the MOSFET, excessive ESD energy can damage the device when the energy is not dissipated rapidly. Therefore, the design of a MOSFET structure plays a key role in reliability. In this study, the influence of different chip size, N+ contact ratios, and gate pad structures on the ESD levels are investigated. The results show that a larger chip size improves energy dissipation, so the ESD level is better. In addition, a higher proportion of the N+ contact area enhances the electron pathways and then ESD levels are improved. Furthermore, more contact area on the top surface of the gate pad polysilicon, along with a smoother structure, may enable the even charge distribution and faster electron discharge and then reduces the electric field at corners, resulting in a higher ESD level.