Mechanical stress in a tapered channel hole of 3D NAND flash memory

Mechanical stress impact according to the taper angle in 3D vertical NAND flash memory (V-NAND) was investigated using technology computer-aided design simulation (TCAD). In the non-tapered V-NAND, the stress of the polysilicon channel is similar regardless of the number of layers and the position of the WL. On the other hand, in tapered V-NAND, as the taper angle decreases, the CD variation of the channel hole increases, and the compressive stress increases close to the lower WL. The compressive stress applied to the polysilicon channel produces a negative threshold voltage shift (ΔVth) due to conduction band lowering. In tapered V-NAND, the lower WL has a larger ΔVth than the upper WL, and a non-uniform Vth shift occurs. However, as the gate length of the tapered V-NAND is scaled down, the stress of the polysilicon channel is decreased, and the stress difference between the lower WL and upper WL is reduced; therefore, the non-uniform Vth shift is suppressed.