计算机科学
静态随机存取存储器
模块化设计
乘数(经济学)
数字信号处理
嵌入式系统
并行计算
量子计算机
加法器
调度(生产过程)
计算
计算机硬件
还原(数学)
辅助存储器
晶体管
逻辑门
量子
处理器调度
随机存取存储器
渡线
托普利兹矩阵
高内存
超大规模集成
非易失性存储器
内存管理
计算机工程
签名(拓扑)
架空(工程)
量化(信号处理)
计算机体系结构
领域(数学分析)
现场可编程门阵列
读写存储器
作者
Tianze Huang,Jiahao Lu,Aobo Li,Lei Chen,Kai Li,Jiaming Zhang,Mingbo Wang,Xianqi Mei,Hao Li,Dongsheng Liu
出处
期刊:IEEE Transactions on Circuits and Systems I-regular Papers
[Institute of Electrical and Electronics Engineers]
日期:2025-01-01
卷期号:: 1-13
标识
DOI:10.1109/tcsi.2025.3605163
摘要
Powerful quantum computers have raised people’s serious concerns on traditional cryptography, leading to great efforts on searching post-quantum alternatives. The screening winner, module lattice-based digital signature algorithm (ML-DSA), is recommended due to good performance and efficiency. However, its hardware implementation exhibits heavy resource burden on logic and memory. This paper presents a lightweight and efficient ML-DSA processor towards resource-constrained applications. The proposed Toeplitz multiplier reduces memory demand with performing specific computations in regular domain representation. Lightweight SHA-3 and samplers alleviate complex connections of large registers through introducing align structure. Diverse modular operations are optimized with shift-and-addition method for decreasing DSP consumption. Moreover, we design a crossover memory scheduling with processing rearrangement to further lower storage requirement. It also enables efficient parallel executions without memory conflict. The ML-DSA processor consumes 15370/7843/7.5/2 LUTs/FFs/BRAMs/DSPs on Artix-7 device and 0.08 mm2 with 27.5 kB SRAM on TSMC 28nm technology. It achieves 51% resource reduction and $4.12\times $ area-time product (ATP) improvement over similar state-of-the-art lightweight implementation.
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