CMOS芯片
功勋
校准
计算机科学
位(键)
电子工程
算法
数学
工程类
统计
计算机安全
计算机视觉
作者
Hao Wei,Peng Zhang,Bibhu Datta Sahoo,Behzad Razavi
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2014-08-01
卷期号:49 (8): 1751-1761
被引量:98
标识
DOI:10.1109/jssc.2014.2313571
摘要
A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of $\hbox{44.4 dB}$ and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology.
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