Warpage and Reliability Challenges for Stacked Silicon Interconnect Technology in Large Packages

Advanced packaging for high end field programmable gate array (FPGA) applications, such as data center and emulation, has recently focused on silicon interposers to enable higher transistor counts and increasing bandwidth, leading to increased power and larger packages, up to 55 mm x 55 mm. The increasing complexity, larger package size, and smaller pitches which enable these advancements pose mechanical challenges such as warpage and reliability. To accommodate the increased power, a stiffener ring may replace the lid. High bandwidth memory (HBM) offers significant performance gain in the form of a vertical stack of memory chips. However, the use of a stiffener ring and incorporation of HBM exacerbate the warpage and reliability challenges, especially as package sizes continue to increase. This work studies the design constraints upon these large packages and to find that reliable packages may be achieved. This work starts by introducing the current options for advanced packaging of an FPGA. The 2.5D silicon interposer structure was selected and the current structure for an FPGA was designed, fabricated, and tested. Warpage was measured with DIC, -40 to 125 °C thermal cycling reliability tests were conducted through 1200 cycles, and high temperature storage tests at 150 °C were conducted for 2000 hours. Through these reliability experiments, the primary mechanical challenges associated with the design space were identified to be thermal cycling and warpage. Finite element models were built and validated using warpage data. Design parameters including ring material, ring size, and substrate CTE were analyzed for their effect on warpage and reliability. Then, a second design was created by optimizing tradeoffs to meet the warpage requirement and improve reliability as much as possible. The second design passed all warpage and reliability requirements.