Design of a 28nm CMOS Self-Biased Ring Oscillator for Intrinsically Robust PVT TRNG

In this paper we present a dynamic entropy generator based on the oscillator jitter, which uses a self-biasing technique to minimize process, voltage, and temperature (PVT) variations. The proposed circuit has the advantage of its intrinsic robustness due to self-biasing design, which eliminates the need of additional calibration steps and simplifies the circuit topology, with a negligible impact in area and power consumption. A frequency deviation below 15 % and a maximum jitter difference of 32 % under PVT variations, is obtained, in a 28 nm CMOS technology circuit prototype. For validation of the proposed circuit technique the IC prototype is compared with a standard ring oscillator and with traditional calibration techniques.