Detailed Analysis and Understanding of the Transport Mechanism of Poly-Si-Based Carrier Selective Junctions

We investigate the transport mechanism of poly-Sibased carrier-selective junctions using the two-dimensional numerical semiconductor device simulations. The detailed transport model considers the charge carrier transport through the pinholes as well as tunneling through a very thin silicon oxide simultaneously. For the verification of the simulation model, the complete temperature dependent transfer length method is modeled and its results are verified with measurements of two different samples. By means of rigorous simulations, the influence of different pinhole geometrical and material parameters on junction resistivity are investigated and explained in detail. From the presented results, the fundamental understanding needed for optimizing the polySi-based carrier selective junction in respect to the main design parameters such as doping level in poly-Si, annealing time, silicon oxide thickness, and pinhole density is given. The detailed analysis shows the pinhole channel plays the most crucial role in the design of poly-Si-based carrier-selective junctions if the silicon oxide layer thickness is larger than 2 nm.