Diffusion-Model-Enhanced Layout Pattern Generation for Sub-3nm DFM

Modern VLSI layout pattern generation for design for manufacturability (DFM) at sub-3 nm nodes faces two challenges: 1) the rapid evolution of intricate design rules; 2) the scarcity of high-quality, rule-compliant layout data during the development of new process technologies. To address these challenges, we introduce a diffusion-based framework that re-frames complex layout synthesis as a sequence of template-guided inpainting tasks, which significantly reduces training sample requirements for legal pattern generation. This approach leverages the knowledge of a pre-trained image foundation model to generate layout variations that satisfy complex 2D metal interconnect design rule constraints, and introduces a novel template-based denoising scheme to eliminate residual noisy pixels. Through few-shot fine-tuning, our approach uniquely produces legal layouts conforming to a full sign-off rule deck at sub-3nm nodes while delivering superior pattern diversity, offering a production-ready, data-efficient solution for next-generation technology node development.