Significant improvement of endurance of Si FeFET through minor hysteresis loop and narrow write pulse width

Abstract The HfO 2 -based Si ferroelectric field-effect transistor has been proposed as an emerging memory device due to its low write power, high speed, CMOS compatibility, and scalability. While the poor endurance limits its application, which is attributed to charge trapping and defect generation. In this work, we investigate the effect of the minor loop operation on defect generation. We find that using a minor loop operation, the trap generation is suppressed, which is quantitively extracted by the low-frequency noise method. We get the endurance of 6 × 10 7 cycles for Si FeFET with a Hf 0.5 Zr 0.5 O 2 ferroelectric layer through minor hysteresis loop operation.