A 0.29 pJ/b 5.27 Tb/s/mm UCIe Advanced Package Link With 2.5-D CoWoS Interposer and a 0.52 pJ/b 0.448 Tb/s/mm UCIe Standard Package Link With Organic Substrate in 3 nm FinFET

This work presents two die-to-die (D2D) wireline transceivers, one compliant with the UCIe advanced package (UCIe-AP) and the other with the UCIe standard package (UCIe-SP) standard, developed in 3 nm FinFET. The Universal Chiplet interconnect express (UCIe)-AP link has 64 RX and 64 TX data lanes in one PHY module and is packaged with a CoWoS interposer, while the UCIe-SP has 16 RX and 16 TX data lanes and is packaged with an organic substrate. Both PHYs support 4–16 Gb/s/pin operation, use a ping-pong RX front end, employ a TX driver that can be configured as ($P+N$)/$N$or$P$/$N$depending on the TX output swing setting, and feature a low latency TX clock domain crossing (CDC) solution. The measurements of the UCIe-AP link were obtained with 8.192Tb/s data traffic on eight links to demonstrate performance in a noisy environment with crosstalk and exhibit 0.29 pJ/bit power efficiency with 5.27Tb/s/mm bandwidth density and 3.5 ns measured FDI-to-FDI latency. The UCIe-AP link has a measured 0.29UI eye opening at 1E-15 BER and 0.03UI at a BER of 1E-27, for 16 Gb/s/pin operation. The UCIe-SP link performance was measured for 5, 15, and 25 mm channel lengths, and yields a 0.448Tb/s/mm beachfront bandwidth density while only consuming 0.52 pJ/bit. Measured FDI-to-FDI latency is 4.0 ns. With a 25 mm organic substrate channel, an aggregate 0.372UI eye opening at BER of 1e−15and 0.108UI at BER of 1e−27is measured at 16 Gb/s/pin operation. A background maintenance mode improves the aggregate eye width (EW) by up to 0.156UI across + 5% to −5% voltage and −40 to 125 C temperaturedrift.