Extraction of Position and Energy Level of Oxide Trap Generating Random Telegraph Noise in 65 nm NOR Flash Memory

The traditional approaches employing random telegraph noise (RTN) to find trap location and energy level are not accurate for the NOR Flash memory due to the asymmetric device structure. In this paper, a new method is proposed to calculate the trap depth, lateral location and trap energy level of 65 nm NOR flash memory. It is found that the trap locates 1.3nm away from Si/SiO2 interface near source side for a fresh memory cell. The new method shows better accuracy with respect to the traditional approaches.