Airgap Integration on Patterned Metal Lines for Advanced Interconnect Performance Scaling

A novel process scheme combining airgap integration with patterned metal lines is introduced. Scheme feasibility is demonstrated on interconnect pitches targeting for 2nm technology node and beyond. Up to 25% coupling capacitance reduction compared to state-of-the-art copper damascene interconnect is achieved by integrating airgap to directly patterned metal lines. Simultaneous line resistance reduction is made possible by proper conductor selection to enable larger grain size and free of metal barrier process required in conventional copper damascene scheme. Performance scalability is demonstrated through the well-controlled airgap height control enabled by the incorporation of a novel airgap formation material removable by thermal process. Finally, scheme robustness is demonstrated through electrical and reliability tests.