The Ultra CSP/sup TM/ wafer scale package

There has been a significant amount of work over the past 5 years on chip scale packaging. The majority of this work has been an extension of conventional IC packaging technology utilizing either wire bonders and/or TAB type packaging technology. Handling discrete devices during the IC packaging for these type of CSPs has resulted in a relatively high cost for these packages and lower IC package yields than desired. This paper presents a new wafer scale packaging technology called the Ultra CSP. Advantages of this wafer scale packaging concept includes commonality with standard IC processing technology for the majority of the packaging process. This paper covers in detail the reliability results achieved for the Ultra CSP on a variety of package sizes and I/O counts covering the range typically seen in microcontrollers, flash and new DRAM architectures. There is also significant discussion on optimization work done on board pad size, solder paste volume and solder paste type.