Stacked chip of Si power device with double side Cu plating for low on-resistance

Stacked chip is the one of the candidate structure to realize low on-resistance, small package. In order to minimize the chip size, it is required to overlap two gate and two source electrodes between two stacked chips, respectively. However, it is impossible to overlap them when wire bonding are used. We completely overlapped these electrodes between two chips by Cu clips. Additionally, double side 20μm Cu plating was applied to the device in order to obtain higher avalanche capable current density of the stacked chip. In this paper, the demonstration results of the chip by using new process are described.