Challenges associated with diamond wire sawing when generating reduced thickness mono-crystalline silicon wafers

Being able to saw and process thinner wafers would allow in principle for further cost reductions in the PV industry if kerf losses can be further reduced and current yield associated with handling and processing of standard thickness wafer can be preserved. In order to enable handling and processing of thinner wafers with high yield, wafer specifications will need to scale appropriately in addition to reducing the thermal and mechanical load experienced during cell and module fabrication. In this work, we identify challenges of sawing thinner wafers down to 100 μm using diamond wire. We also report the characterization of the `as-cut' wafers via TTV, bow, surface roughness, reflectance, and the presence of cracks for the different wafer thicknesses.