Cost-Effective 1200 V SiC MOSFETs on a Novel 150 mm SiC Engineered Substrate with Dummy-Grade Material Reuse

The SiC substrate cost accounts for >50% of final device cost, and its manufacturing suffers from a high carbon footprint. To address this challenge, this work demonstrates a novel 150 mm single-crystal SiC engineered substrate, which homogeneously integrates a prime-grade SiC layer onto a dummy-grade SiC substrate by surface-active bonding. This engineered substrate reuses low-grade SiC substrates, which are often disposed as wastes in the MOSFET industrial production, as well as recycling the high-grade wafer for over 30 times. It thus can enable a drastic reduction in the substrate cost (by ~40%) and the associated carbon footprint. The engineered substrate demonstrates a defect density as low as prime-grade substrate, a low thermal boundary resistance (TBR) of 2.8 m²K/GW, as well as very small electric field at the bonded interface. The TBR is among the lowest reported for the SiC interfaces bonded with SiC, GaN, and $\text{Ga}_{2}\mathrm{O}_{3}$. The 150 mm, 1200 V-class SiC epi grown on this substrate achieved a high killer-defect-free yield of 99.2%. The 1200 V, 20 $\mathrm{m}\Omega$ SiC MOSFETs fabricated on this 150 mm epi demonstrate a yield over 70% (for $I_{\text{DSS}} < 2\mu A$. at 1200V), as well as a performance and reliability comparable to the state-of-the-art commercial devices. Circuit robustness tests reveal no degradation of the bonding interface under a >250 A, 10 ms surge current. To the best of our knowledge, this is the first report of the wafer-level device data and high-current robustness for a SiC engineering substrate. These results show the great potential of this new substrate technology to enable more economical and sustainable SiC power electronics.