Exploring FinFET and Gate-All-Around FET for SRAM Cell Arrays at the 3 nm Process Node

Improving transistor performance is increasingly challenging as technology nodes continue to scale, putting pressure on the limitations of the current industry-dominant transistor model and interconnect material. To find alternative options for more advanced nodes, we investigate the performance of Gate-All-Around Field-Effect Transistor (GAAFET) and Fin-Shaped Field-Effect Transistor (FinFET) devices in Static Random Access Memory (SRAM) cell arrays at the 3nm process node. This paper also presents a comparative study of Back-End-of-Line (BEOL) options from the 7nm to 3nm node. Combining the modeling and simulations of the two device structures and interconnect options, we can extract the necessary parameters for SRAM cell simulation with varied processes in NVSim. Further, we found that the alternative interconnect option was more significant in improving the performance of SRAM cell read/write latency than using a different transistor model.