Improved Frequency Response of Two Stage Amplifier using Cascode Current Mirror and Voltage Buffer Circuit

In an effort to enhance the amplifier's frequency response, this study presents a two-stage design that includes a voltage buffer and cascode current mirror. The proposed design achieves a gain of 75.3 dB, a Gain Bandwidth Product (GBW) of 14.4 MHz, and a phase margin (PM) of 50°. Furthermore, it exhibits a 77.6 dB Common Mode Rejection Ratio (CMRR) and a Power Supply Rejection Ratio (PSRR) of 63.24 dB. Tanner Tool with TSMC 0.18 μm CMOS technology is used to run the simulation.